Non-volatile memories (NVMs) have a major role in current semiconductor products either as stand alone devices or embedded applications such as onboard a chip having logic. A large percentage of microcontrollers include such an NVM. Typically such NVMs have a floating gate for each memory device. An alternative becoming available is using nanocrystals for the charge storage layer which offers improved reliability but has a smaller memory window in that there is less differential between the programmed and erased states. A primary cause of this is that during erase, electrons are back-injected into the charge storage layer. For erase, the control gate, in an NMOS memory cell, which is the typical, is biased with a negative voltage with respect to the substrate to push electrons out of charge storage layer to the substrate. Since the control gate is typically doped to the same conductivity type as the source and drain, the negative bias also pushes electrons from the control gate to the storage layer. There reaches a point during erase at which the rate of removal electrons from the storage layer is the same as the rate of electrons arriving at the charge layer from the gate. When this occurs no further erasing is occurring even though a net balance of electrons remains in the charge storage layer. This phenomenon is also present to an even greater extent in silicon-oxide-nitride oxide-silicon (SONOS) memory cells.
A known approach to reduce this back-injection is to use a P-doped gate with the N-type source/drains. This device is difficult to manufacture, however, because the gate is preferably used as a mask during the source/drain implant so that the gate receives the same doping as the source/drains unless special masking steps are undertaken. The additional masking tends to make the source/drain not self-aligned to the gate. Thus, there is a need for improved techniques in achieving control gates doped to a different conductivity type than the source/drains.